It is conventional to include an input buffer between an input pad and the components of an electronic circuit. It is desirable to include some form of protection to ensure that the input voltage to the input buffer is not outside the range of voltages for which the input buffer is designed. If the voltage applied to the input buffer is outside the voltage range for which the input buffer is designed, there is a risk that the transistors forming the input buffer circuitry will be stressed.
Typically, over voltage protection is achieved by the use of an NMOS pass transistor which is connected between the input pad and the input buffer. The gate of the NMOS pass transistor is connected to a normal signal voltage. If the voltage applied to the pad is greater that the maximum input voltage, the voltage applied to the input of the input buffer is limited by the threshold drop of the transistor. However, the use of an NMOS pass transistor means that there is a reduction in the input voltage applied to the input buffer even when the voltage is within a normal range. Therefore, when the input voltage corresponds to a high logic, the voltage applied to the input buffer will be less than the normal maximum input voltage. This can result in duty cycle distortion.
Furthermore, the use of a pass transistor is not able to compensate for under voltages. Indeed, when the voltage is below a normal lower signal level, the gate oxide of the pass transistor itself will be stressed.
It would be advantageous to be able to provide a voltage protection circuit which is able to protect an input buffer from under voltages and over voltages in the transmission line without unduly compromising the performance of the device, for example, in terms of duty cycle and operation speed, and without unduly stressing the transistors of the protection circuit or of the input buffer.